Designers and manufacturers of electronic devices are continually searching for ways to reduce the size of electronic components. Some recent developments involve the use of solder connections for electrically interconnecting semiconductor chips to printed circuit boards ("PCB") in order to use the space on the PCB more efficiently. Solder connections have proven to be somewhat effective; however, the differences in thermal expansion and contraction ("thermal mismatch") between the semiconductor chip and the PCB places a great amount of stress on the solder and may adversely effect the integrity of the numerous solder bonds required to make an electrical connection. Warpage of either the semiconductor chip or the PCB may also have a negative effect on the integrity of the solder connections.
There have been a number of prior art solutions attempting to reduce the stress on solder joints caused by thermal mismatch. One solution put forth in U.S. Pat. No. 4,642,889 teaches embedding wires within each solder column to reinforce the solder, thereby allowing higher solder pedestals and more elasticity. Another solution includes spirally wrapping wire around the outside of the solder. A further solution put forth in U.S. Pat. No. 5,316,788 includes providing a combination of solder and high-lead solder. Still other prior art solutions make use of an underfill material disposed between the semiconductor chip and the supporting substrate which allows the stress caused by the thermal mismatch to be more uniformly spread out over the entire surface of the solder connection. All of these prior art solutions are aimed at improving the reliability of solder connections; however, each of these solutions encounters significant problems such as insufficient compliancy between the semiconductor chip and the PCB.
Several inventions, commonly assigned to the assignee of the present invention, deal effectively, with the thermal mismatch problem. For example, U.S. Pat. No. 5,148,266 discloses improvements in semiconductor chip assemblies and methods of making the same. In certain embodiments of the '266 patent, a semiconductor chip can be connected to a substrate using a sheet-like, and preferably flexible, interposer. The interposer overlies the top, contact-bearing surface of the chip. A first surface of the interposer faces towards the chip whereas a second surface faces away from the chip. Electrical terminals, which can be bonded to a substrate, are provided on the second surface of the interposer, and the interposer is provided with apertures extending through it. Flexible leads extend through the apertures, between. the terminals on the second surface of the interposer and the contacts on the chip. Because the terminals are movable relative to the contacts on the chip, the arrangements described in the '266 patent provide excellent resistance to differential expansion of the chip relative to the substrate caused by thermal cycling. The interposer disclosed in the '266 patent may also include a compliant layer disposed between the terminals and the chip.
Commonly assigned U.S. patent application Ser. No. 08/123,882, filed Sep. 20, 1993 (now U.S. Pat. No. 5,477,611), the disclosure of which is incorporated herein by reference, discloses a method for creating an interface between a chip and chip carrier including spacing the chip a given distance above the chip carrier, and introducing a liquid in the gap between the chip and carrier. Preferably, the liquid is a curable material which is cured into a resilient layer such as an elastomer after its introduction into the gap. In a preferred embodiment, the terminals on a chip carrier are planarized or otherwise vertically positioned by deforming the terminals into set vertical locations with a plate, and a liquid is then cured between the chip carrier and chip.
Copending, commonly assigned U.S. patent application Ser. No. 08/365,699 entitled "Compliant Interface for a Semiconductor Chip and Method Therefor" filed Dec. 29, 1994, now U.S. Pat. No. 5,659,952, the disclosure of which is incorporated herein by reference, discloses a method of fabricating a compliant interface for a semiconductor chip, typically comprised of a compliant encapsulation layer having a controlled thickness. In certain preferred methods according to the '699 application, a first support structure, such as a flexible, substantially inextensible dielectric film, is provided. A resilient element, such as a plurality of compliant pads, is attached to a first surface of the first support structure, with any two adjacent compliant pads defining a channel therebetween. Attaching the compliant pads to the first support structure may be accomplished in a number of different ways. In one embodiment, a stencil mask having a plurality of holes extending therethrough is placed on top of the first surface of the support structure. The holes in the mask are then filled with a curable liquid, such as a silicone. After the mask has been removed, the curable liquid is at least partially cured to form an elastomer, such as by heating or by exposure to ultraviolet light. Thus, there is provided an assembly which includes a plurality of compliant pads having channels between adjacent pads.
In a further preferred embodiment of the '699 application, the assembly including the plurality of compliant pads is used with a second support structure such as a semiconductor chip having a plurality of contacts on a first surface. The first surface of the chip is abutted against the plurality of compliant pads and the contacts are electrically connected to a corresponding plurality of terminals on a second side of the support structure. Typically, the first surface of the chip is pressed against the array of compliant pads by a platen engaged with the terminals, thereby assuring the planarity of the first support structure, or flexible dielectric film. A compliant filler such as a curable liquid is then injected into the channels between the chip and the support structure and around the compliant pads while the chip and support structure are held in place. The filler may then be cured to form a substantially uniform, planar, compliant layer between the chip and the support structure. Preferred embodiments of the '699 application provide a compliant, planar interface which effectively accommodates for the thermal coefficient of expansion mismatch between the chip and a supporting substrate thereby alleviating much of the stress on the connections therebetween. Further, the combination provides an effective encapsulation barrier against moisture and contaminants.
Commonly assigned U. S. Pat. No. 5,548,091 describes other methods of bonding compliant elements to the chip and support structure using adhesives. In certain preferred methods according to the '091 patent, a support structure such as a dielectric film is provided with a prefabricated compliant layer. The compliant layer in turn has an adhesive on its surface remote from the dielectric film. The semiconductor chip is placed in contact with the adhesive, and the adhesive is activated to bond the chip to the compliant layer. The adhesive may be provided in a non-uniform layer to facilitate release of air during the bonding process and thus prevent void formation. Known adhesives tend to delaminate from the resilient element under the extreme stresses of temperature and humidity and also under stress of extreme thermal mismatch. Accordingly, still further improvements directed toward providing a resilient element that can be more effectively bonded to microelectronic elements using known adhesives would be desirable.
Despite the positive results of the aforementioned commonly owned inventions, the disclosures of which are incorporated herein by reference, still further improvements would be desirable.